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? semiconductor components industries, llc, 2015 july, 2015 ? rev. 2 1 publication order number: ncp1607/d ncp1607 cost effective power factor controller the ncp1607 is an active power factor controller specifically designed for use as a pre?converter in ac?dc adapters, electronic ballasts, and other medium power off line converters (typically up to 250 w). it utilizes critical conduction mode (crm) to ensure unity power factor across a wide range of input voltages and power levels. the ncp1607 minimizes the number of external components. the integration of comprehensive safety protection features makes it an excellent choice for designing robust pfc stages. it is available in a soic?8 package. general features ? ?unity? power factor ? no need for input voltage sensing ? latching pwm for cycle by cycle on time control (voltage mode) ? high precision voltage reference ( 1.6% over the temperature range) ? very low startup current consumption ( 40 a) ? low typical operating current (2.1 ma) ? source 500 ma / sink 800 ma totem pole gate driver ? undervoltage lockout with hysteresis ? pin to pin compatible with industry standards ? this is a pb?free device ? this device uses halogen?free molding compound safety features ? programmable overvoltage protection ? open feedback loop protection ? accurate and programmable on time control ? accurate overcurrent detector typical applications ? ac?dc adapters, tvs, monitors ? off line appliances requiring power factor correction ? electronic light ballast figure 1. typical application + ac line emi filter 1 4 3 2 8 5 6 7 + c bulk load (ballast, smps, etc.) ncp1607 v out r s c in r zcd r out1 r out2 c comp v cc c t d boost l boost fb control ct cs gnd zcd drv v cc www. onsemi.com so?8 d suffix case 751 marking diagrams pin connection 1 8 a = assembly location l = wafer lot y = year w = work week = pb?free package 1607b alyw 1 8 fb control ct cs v cc drv gnd zcd (top view) device package shipping ? ordering information ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification s brochure, brd801 1/d. ncp1607bdr2g soic?8 (pb?free) 2500 / tape & ree l
ncp1607 www. onsemi.com 2 figure 2. block diagram uvlo drv gnd fb control cs zcd e/a + ? measure + + + + + v cl(pos) clamp shutdown demag uvp fault ocp + ? + dynamic ovp shutdown v eah clamp active clamp leb add v eal offset static ovp is triggered when clamp is activated. v eal clamp static ovp off timer reset pwm r q s (enable ea) + r q s r q s r q s r q s ac in drv v control r out2 r out1 c comp r s r zcd c bulk q q q v cc v out v cc q q v dd v dd i charge v dd v cc v dd v ddgd v dd reg i easink i sink >i ovp v cl(neg) *all sr latches are reset dominant + ? + ? + ? + ? + ? enable + ? v cs(limit) d boost l boost uv dd uv dd uv dd v ddgd uvlo r fb v ref v uvp p ok p ok v zcdh v zcdl v sdl p ok c t c t esd esd esd esd
ncp1607 www. onsemi.com 3 pin function description pin name function 1 fb the fb pin is the inverting input of the internal error amplifier. an external resistor divider scales the output voltage to th e internal reference voltage to maintain regulation. the feedback information is also used for the programmable overvoltage and undervoltage protections. the controller is disabled when this pin is below the undervoltage protection threshold, v uvp , typically 0.3 v. 2 control the control pin is the output of the internal error amplifier. a compensation network is placed between the control and fb pins to set the loop bandwidth. a low enough bandwidth is needed to obtain a high power factor ratio and a low thd. 3 ct the ct pin sources a current to charge an external timing capacitor. the circuit controls the power switch on time by com- paring the ct voltage to an internal voltage derived from the regulation block. the ct pin discharges the external timing capacitor at the end of the switching cycle. 4 cs the cs pin limits the cycle?by?cycle current through the power switch. when the cs voltage exceeds the internal thresh- old, the mosfet driver turns off. the sense resistor that connects to the cs pin programs the maximum switch current. 5 zcd the voltage of an auxiliary winding is applied to this pin to detect when the inductor is demagnetized for critical conduction mode operation. the controller is disabled when this pin is grounded. 6 gnd analog ground. 7 drv integrated mosfet driver capable of driving a high gate charge power mosfet. 8 v cc the v cc pin is the positive supply of the controller. the controller is enabled when v cc exceeds v cc(on) and remains enabled until v cc decreases below v cc(off) . maximum ratings rating symbol value unit supply v oltage v cc ?0.3 to 20 v supply current i cc 20 ma drv voltage v drv ?0.3 to 20 v drv sink current i drv(sink) 800 ma drv source current i drv(source) 500 ma fb voltage v fb ?0.3 to 10 v fb current i fb 10 ma control v oltage v control ?0.3 to 10 v control current i control ?2 to 10 ma ct voltage v ct ?0.3 to 6 v ct current i ct 10 ma cs voltage v cs ?0.3 to 6 v cs current i cs 10 ma zcd voltage v zcd ?0.3 to 10 v zcd current i zcd 10 ma power dissipation and thermal characteristics d suffix, plastic package, case 751 maximum power dissipation @ t a = 70 c thermal resistance junction?to?air p d (so) r ja (so) 450 178 mw c/w operating junction temperature range t j ?40 to 125 c maximum junction t emperature t j(max) 150 c storage temperature range t stg ?65 to 150 c lead temperature (soldering, 10 s) t l 300 c stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be af fected. 1. this device series contains esd protection and exceeds the following tests: pins 1 ? 8: human body model 2000 v per jedec standard jesd22?a1 14e, charged device model 1000 v per jedec standard jesd22?c101e. 2. this device contains latch?up protection and exceeds 100 ma per jedec standard jesd78.
ncp1607 www. onsemi.com 4 electrical c haracteristics (for typical values, t j = 25 c. for min/max values, t j = ?40 c to +125 c, unless otherwise specified, v cc = 12 v, v fb = 2.4 v, v cs = 0 v, v control = open, v zcd = open, c drv = 1 nf, c t = 1 nf) characteristics symbol min typ max unit v cc undervoltage lockout section v cc startup threshold (undervoltage lockout threshold, vcc rising) ?25 c < t j < +125 c ?40 c < t j < +125 c v cc(on) 11.0 10.9 11.8 11.8 13.0 13.1 v v cc disable voltage after turn on (undervoltage lockout threshold, v cc falling) ?25 c < t j < +125 c ?40 c < t j < +125 c v cc(off) 8.7 8.5 9.5 9.5 10.3 10.5 v undervoltage lockout hysteresis h uvlo 2.2 2.5 2.8 v device consumption i cc consumption during startup: 0 v < v cc < v cc(on) ? 200 mv i cc(startup) ? 23.5 40 a i cc consumption after turn on at no load, 70 khz switching i cc1 ? 1.4 2.0 ma i cc consumption after turn on at 70 khz switching i cc2 ? 2.17 3.0 ma i cc consumption after turn on at no switching (such as during ovp fault, uvp fault, or grounding zcd) i cc(fault) ? 1.2 1.6 ma regulation block (error amplifier) voltage reference t j = 25 c ?25 c < t j < +125 c ?40 c < t j < +125 c v ref 2.475 2.465 2.460 2.50 2.50 2.50 2.525 2.535 2.540 v v ref line regulation from v cc(on) + 200 mv < v cc < 20 v, t j = 25 c v ref (line) ?2.0 ? 2.0 mv error amplifier current capability: (note 3) sink (v control = 4 v, v fb = 2.6 v): source (v control = 4 v, v fb = 2.4 v): i ea 8.0 ?2.0 17 ?6.0 ? ? ma error amplifier open loop dc gain (note 4) g ol ? 80 ? db unity gain bandwidth (note 4) bw ? 1.0 ? mhz fb bias current (v fb = 2.5 v) i fb 0.25 0.53 1.25 a fb pull down resistor (v fb = 2.5 v) r fb 2.0 4.7 10 m control pin bias current (fb = 0 v and v control = 4.0 v) i control ?1.0 ? 1.0 a v control (i easo urce = 0.5 ma, v fb = 2.4 v) v eah 4.9 5.3 5.7 v v control (i easink = 0.5 ma, v fb = 2.6 v) v eal 1.85 2.1 2.4 v v ea(diff) = v eah ? v eal v ea(diff) 3.0 3.2 3.4 v current sense block overcurrent volta ge threshold v cs(limit) 0.45 0.5 0.55 v leading edge blanking duration t leb 150 256 350 ns overcurrent v oltage propagation delay t cs 40 100 170 ns cs bias current (v cs = 2 v) i cs ?1.0 ? 1.0 a zero current detection zero current detection threshold (v zcd rising) v zcdh 1.9 2.1 2.3 v zero current detection threshold (v zcd falling) v zcdl 1.45 1.6 1.75 v v zcdh ? v zcdl v zcd(hys) 300 500 800 mv maximum zcd bias current (v zcd = 5 v) i zcd ?2.0 ? +2.0 a upper clamp voltage (i zcd = 2.5 ma) v cl(pos) 5.0 5.7 6.5 v current capability of the positive clamp at v zcd = v cl(pos) + 200 mv: i cl(pos) 5.0 8.5 ? ma negative active clamp voltage (i zcd = ?2.5 ma) v cl(neg) 0.45 0.6 0.75 v 3. parameter values are valid for transient conditions only. 4. parameter characterized and guaranteed by design, but not tested in production.
ncp1607 www. onsemi.com 5 electrical c haracteristics (for typical values, t j = 25 c. for min/max values, t j = ?40 c to +125 c, unless otherwise specified, v cc = 12 v, v fb = 2.4 v, v cs = 0 v, v control = open, v zcd = open, c drv = 1 nf, c t = 1 nf) characteristics unit max typ min symbol current capability of the negative active clamp: in normal mode (v zcd = 300 mv) in shutdown mode (v zcd = 100 mv) i cl(neg) 2.5 35 3.7 70 5.0 100 ma a shutdown threshold (v zcd falling) v sdl 150 205 250 mv enable threshold (v zcd rising) v sdh ? 290 350 mv shutdown comparator hysteresis v sd(hys) ? 85 ? mv zero current detection propagation delay t zcd ? 100 170 ns minimum detectable zcd pulse width t sync ? 70 ? ns drive off restart timer t start 75 179 300 s ramp control ct charge current (v ct = 0 v) ?25 c < t j < +125 c ?40 c < t j < +125 c i charge 243 235 270 270 297 297 a time to discharge a 1 nf ct capacitor from v ct = 3.4 v to 100 mv. t ct(discharge) ? ? 100 ns maximum ct level before dr v switches off ?25 c < t j < +125 c ?40 c < t j < +125 c v ctmax 2.9 2.9 3.2 3.2 3.3 3.4 v pwm propagation delay t pwm ? 142 220 ns over and undervoltage protection dynamic overvoltage protection (ovp) triggering current: t j = 25 c t j = ?40 c to +125 c i ovp 9.0 8.7 10.5 ? 11.8 12.1 a hysteresis of the dynamic ovp current before the ovp latch is released i ovp(hys) ? 8.5 ? a static ovp threshold voltage v ovp ? v eal + 100 mv ? v undervoltage protection (uvp) threshold v oltage v uvp 0.25 0.302 0.4 v gate drive section gate drive resistance: r oh @ i source = 100 ma r ol @ i sink = 100 ma r oh r ol ? ? 12 6.0 18 10 drive voltage rise time from 10% v cc to 90% v cc t rise ? 30 80 ns drive voltage fall time from 90% v cc to 10% v cc t fall ? 25 70 ns driver output voltage at v cc = v cc(on) ? 200 mv and i sink = 10 ma v out(start) ? ? 0.2 v 3. parameter values are valid for transient conditions only. 4. parameter characterized and guaranteed by design, but not tested in production. product parametric performance is indicated in the electrical characteristics for the listed test conditions, unless otherwise noted. product performance may not be indicated by the electrical characteristics if operated under different conditions.
ncp1607 www. onsemi.com 6 typical characteristics figure 3. ct charge current vs. t emperature figure 4. on time vs. v control level temperature ( c) v control (v) 150 100 75 50 25 0 ?25 ?50 260 262 264 266 268 270 272 274 6 5 4 3 2 1 0 0 2 4 6 8 10 12 14 i charge , ct charge current ( a) t on , on time ( s) 125 ct = 1 nf figure 5. maximum ct level vs. t emperature figure 6. pwm propagation delay vs. temperature temperature ( c) temperature ( c) 125 100 75 50 25 0 ?25 ?50 3.00 3.05 3.15 3.20 3.25 3.30 125 100 75 50 25 0 ?25 ?50 130 140 150 160 170 v ctmax , maximum ct level (v) t pwm , pwm propagation delay (ns) 3.10 150 150 figure 7. reference voltage vs. temperature figure 8. error amplifier open loop gain and phase temperature ( c) frequency (hz) 125 100 75 50 25 0 ?25 ?50 2.470 2.475 2.480 2.485 2.490 2.495 2.500 2.505 10m 1m 100k 10k 1k 100 10 ?20 0 20 40 60 80 100 v ref , reference voltage (v) g ol , open loop gain (db) 150 phase ( ) 200 160 120 80 40 0 ?40 gain phase
ncp1607 www. onsemi.com 7 typical characteristics figure 9. dynamic ovp triggering current vs. temperature temperature ( c) 125 100 75 50 25 0 ?25 ?50 7 8 9 10 11 12 i ovp , dynamic ovp triggering current ( a) 150 i ovp(hys) i ovp temperature ( c) temperature ( c) 125 100 75 50 25 0 ?25 ?50 2.00 2.05 2.10 2.15 2.20 2.25 2.30 125 100 75 50 25 0 ?25 ?50 26 14 16 18 20 22 24 temperature ( c) temperature ( c) 150 125 100 75 25 0 ?25 ?50 8 9 10 11 12 13 125 100 75 50 25 0 ?25 ?50 160 170 180 190 200 i cc2 , switching supply current (ma) i cc(startup) , startup current ( a) v cc , supply voltage threshold (v) t start , restart timer ( s) 150 15 0 50 v cc(on) v cc(off) 15 0 figure 10. feedback resistor vs. temperature 0 1 2 3 4 5 6 7 ?50 ?25 0 25 50 75 100 125 15 0 temperature ( c) r fb , feedback resistor (m ) figure 11. switching supply current vs. temperature figure 12. startup current vs. temperature figure 13. supply voltage thresholds vs. temperature figure 14. restart t imer vs. temperature
ncp1607 www. onsemi.com 8 typical characteristics figure 15. gate drive resistance vs. temperature figure 16. leb duration vs. temperature temperature ( c) temperature ( c) 125 100 75 50 25 0 ?25 ?50 0 2 4 8 10 12 16 18 125 100 75 50 25 0 ?25 ?50 240 250 260 270 280 r oh/ol , gate drive resistance ( ) t leb , leb duration (ns) 6 14 150 r oh r ol 15 0 figure 17. overcurrent threshold voltage vs. temperature temperature ( c) 125 100 75 50 25 0 ?25 ?50 figure 18. undervoltage protection threshold voltage vs. temperature figure 19. shutdown thresholds vs. temperature temperature ( c) temperature ( c) 1 50 125 100 75 25 0 ?25 ?50 0.280 0.285 0.305 0.310 0.315 0.320 125 100 75 50 25 0 ?25 ?50 0.15 0.20 0.25 0.30 0.35 v cs(limit) , overcurrent threshold voltage (v) v uvp , uvp threshold voltage (v) v sdh/sdl , shutdown threshold (v) 150 50 150 0.520 0.515 0.510 0.505 0.500 0.495 0.490 0.485 0.480 0.290 0.295 0.300 v sdh v sdl i source = 100 ma i sink = 100 ma
ncp1607 www. onsemi.com 9 introduction the ncp1607 is a voltage mode power factor correction (pfc) controller designed to drive cost effective pre?converters to meet input line harmonic regulations. this controller operates in critical conduction mode (crm) for optimal performance in applications up to 250 w. its voltage mode scheme enables it to obtain unity power factor without the need for a line sensing network. the output voltage is accurately controlled by a high precision error amplifier. the controller also implements a comprehensive array of safety features for robust designs. the key features of the ncp1607 are as follows: ? constant on time (voltage mode) crm operation. high power factor ratios are easily obtained without the need for input voltage sensing. this allows for optimal standby power consumption. ? accurate and programmable on time limitation. the ncp1607 uses an accurate current source and an external capacitor to generate the on time. ? high precision voltage reference. the error amplifier reference voltage is guaranteed at 2.5 v 1.6% over process, temperature, and voltage supply levels. this results in very accurate output voltages. ? very low startup current consumption. the circuit consumption is reduced to a minimum (< 40 a) during the startup phase, allowing fast, low loss, charging of v cc . the architecture of the ncp1607 gives a controlled undervoltage lockout level and provides ample v cc hysteresis during startup. ? powerful output driver. a source 500 ma / sink 800 ma totem pole gate driver is used to provide rapid turn on and turn off times. this allows for improved efficiencies and the ability to drive higher power mosfets. additionally, a combination of active and passive circuitry is used to ensure that the driver output voltage does not float high while v cc is below its turn on level. ? programmable overvoltage protection (ovp). the adjustable ovp feature protects the pfc stage against excessive output overshoots that could damage the application. these events can typically occur during the startup phase or when the load is abruptly removed. ? protection against open feedback loop (undervoltage protection). undervoltage protection (uvp) disables the pfc stage when the output voltage is excessively low. this also protects the circuit in case of a failure in the feedback network: if no voltage is applied to fb because of a poor connection or if the fb pin is floating, uvp is activated shutting down the converter. ? overcurrent limitation. the peak current is accurately limited on a pulse by pulse basis. the level is adjustable by modifying the current sense resistor. an integrated leb filter reduces the chance of noise prematurely triggering the overcurrent limit. ? shutdown features. the pfc pre?converter is placed in a shutdown mode by grounding the fb pin or the zcd pin. during this mode, the i cc current consumption is reduced and the error amplifier is disabled. application information most electronic ballasts and switching power supplies use a diode bridge rectifier and a bulk storage capacitor to produce a dc voltage from the utility ac line (figure 20). this dc voltage is then processed by additional circuitry to drive the desired output. figure 20. t ypical circuit without pfc load converter rectifiers bulk storage capacitor + ac line this simple rectifying circuit draws power from the line when the instantaneous ac voltage exceeds the capacitor voltage. since this occurs near the line voltage peak, the resulting current draw is non sinusoidal and contains a very high harmonic content. this results in a poor power factor (typically < 0.6) and consequently, the apparent input power is much higher than the real power delivered to the load. additionally, if multiple devices are tied to the same input line, the effect is magnified and a ?line sag? effect can be produced (see figure 21). figure 21. typical line waveforms without pfc line sag rectified dc ac line v oltage ac line current 0 0 v pk increasingly, government regulations and utility requirements necessitate control over the line current harmonic content. to meet this need, power factor correction is implemented with either a passive or active circuit. passive circuits usually contain a combination of large capacitors, inductors, and rectifiers that operate at the ac line frequency. active circuits incorporate some form of a high frequency switching converter that regulates the
ncp1607 www. onsemi.com 10 input current to stay in phase with the input voltage. these circuits operate at a higher frequency and so they are smaller, lighter in weight, and more efficient than a passive circuit. with proper control of an active pfc stage, almost any complex load can be made to appear in phase with the ac line, thus significantly reducing the harmonic current content. because of these advantages, active pfc circuits have become the most popular way to meet harmonic content requirements. generally, they consist of inserting a pfc pre?regulator between the rectifier bridge and the bulk capacitor (figure 22). figure 22. active pfc pre?converter with the ncp1607 rectifiers + ac line high frequency bypass capacitor ncp1607 pfc preconverter converter load + bulk storage capacitor the boost (or step up) converter is the most popular topology for active power factor correction. with the proper control, it produces a constant voltage while drawing a sinusoidal current from the line. for medium power (<300 w) applications, critical conduction mode (also called borderline conduction mode) is the preferred control method. critical conduction mode (crm) occurs at the boundary between discontinuous conduction mode (dcm) and continuous conduction mode (ccm). in crm, the next driver on time is initiated when the boost inductor current reaches zero. crm operation is an ideal choice for medium power pfc boost stages because it combines the lower peak currents of ccm operation with the zero current switching of dcm operation. the operation and waveforms in a pfc boost converter are illustrated in figure 23. figure 23. schematic and waveforms of an ideal crm boost converter diode bridge in + ? l diode bridge in + ? l + the power switch is on the power switch is off critical conduction mode: next current cycle starts as soon as the core is reset. coil current + with the power switch voltage being about zero, the input voltage is applied across the coil. the coil current linearly increases with a (v in /l) slope. the coil current flows through the diode. the coil voltage is (v out ? v in ) and the coil current linearly decays with a (v out ? v in )/l slope. v out (v out ? v in )/l i l(pk) i l v in v drain v drain v in /l v out v in if next cycle does not start then v drain rings towards v in + i l v in v drain
ncp1607 www. onsemi.com 11 when the switch is closed, the inductor current increases linearly to its peak value. when the switch opens, the inductor current linearly decreases to zero. at this point, the drain voltage of the switch (v d ) is essentially floating and begins to drop. if the next switching cycle does not start, then the voltage will ring with a dampened frequency around v in . a simple derivation of equations (such as found in and8123), leads to the result that good power factor correction in crm opera tion is achieved when the on time is constant across an ac cycle and is equal to: t on 2 p out l vac 2 (eq. 1) a simple plot of this switching over an ac line cycle is illustrated in figure 24. the off time varies based on the instantaneous line voltage, but the on time is kept constant. this naturally causes the peak inductor current (i l(pk) ) to follow the ac line voltage. the ncp1607 represents an ideal method to implement this constant on time crm control in a cost effective and robust solution. the device incorporates an accurate regulation circuit, a low power startup circuit, and advanced protection features. figure 24. inductor waveform during crm operation on off mosfet i in (t) i l (t) v in (t) v in(pk) i l(pk) i in(pk) error amplifier regulation the ncp1607 is configured to regulate the boost output voltage based on its built in error amplifier (ea). the error amplifier ?s negative terminal is pinned out to fb, the positive terminal is tied to a 2.5 v 1.6% reference, and the output is pinned out to control (figure 25). figure 25. error amplifier and on time regulation circuits fb control + ? ea + pwm block v control r out2 r out1 c comp t pwm t on(max) v out t on v eal v eah slope ct i charge v control r fb v ref a resistor divider from the boost output to the input of the ea sets the fb level. if the output voltage is too low, then the fb level will drop and the ea will cause the control voltage to increase. this increases the on time of the driver, which increases the power delivered and brings the output back into regulation. alternatively, if the output voltage (and hence fb voltage) is too high, then the control level decreases and the driver on times are shortened. in this way, the circuit regulates the output voltage (v out ) so that the v out portion that is applied to fb through the resistor divider r out1 and r out2 is equal to the internal reference (2.5 v). the output voltage is set using equation 2: v out v ref r out1 r eq r eq (eq. 2) where r eq is the parallel combination of r out2 and r fb . r eq is calculated using equation 3: r eq r out2 r fb r out2 r fb (eq. 3)
ncp1607 www. onsemi.com 12 a compensation network is placed between the fb and control pins to reduce the speed at which the ea responds to changes in the boost output. this is necessary due to the nature of an active pfc circuit. the pfc stage absorbs a sinusoidal current from a sinusoidal line voltage. hence, the converter provides the load with a power that matches the average demand only. therefore, the output capacitor must ?absorb? the difference between the delivered power and the power consumed by the load. this means that when the power fed to the load is lower than the demand, the output capacitor discharges to compensate for the lack of power. alternatively, when the supplied power is higher than that absorbed by the load, the output capacitor charges to store the excess energy. the situation is depicted in figure 26. figure 26. output voltage ripple for a constant output power v out p out p in iac vac as a consequence, the output voltage exhibits a ripple at a frequency of either 100 hz (for 50 hz mains such as in europe) or 120 hz (for 60 hz mains in the usa). this ripple must not be taken into account by the regulation loop because the error amplifier?s output voltage must be kept constant over a given ac line cycle for a proper shaping of the line current. due to this constraint, the regulation bandwidth is typically set below 20 hz. for a simple type 1 compensation network, only a capacitor is placed between fb and control (see figure 1). in this configuration, the capacitor necessary to attenuate the bulk voltage ripple is given by: c comp 10 g 20 4 f line r out1 (eq. 4) where g is the attenuation level in db (commonly 60 db) on time sequence since the ncp1607 is designed to control a crm boost converter, its switching pattern must accommodate constant on times and variable off times. the controller generates the on time via an external capacitor connected to pin 3 (ct). a current source charges this capacitor to a level determined by the control pin voltage. specifically, ct is charged to v control minus the v eal offset (2.1 v typical). once this level is exceeded, the drive is turned off (figure 27). figure 27. on time generation control ct + ? pwm + drv i charge t on v eal v control ? v eal t on v ct v ct(off) v dd drv v control since v control varies with the rms line level and output load, this naturally satisfies equation 1. and if the values of compensation components are sufficient to filter
ncp1607 www. onsemi.com 13 out the bulk voltage ripple, then this on time is truly constant over the ac line cycle. note that the maximum on time of the controller occurs when v control is at its maximum. therefore, the ct capacitor must be sized to ensure that the required on time can be delivered at full power and the lowest input voltage condition. the maximum on time is given by: t on(max) ct v ctmax i charge (eq. 5) combining this equation with equation 1, gives: ct 2 p out l i charge vac 2 v ctmax (eq. 6) where v ctmax = 2.9 v (min) i charge = 297 a (max) off time sequence while the on time is constant across the ac cycle, the off time in crm operation varies with the instantaneous input voltage. the ncp1607 determines the correct off time by sensing the inductor voltage. when the inductor current drops to zero, the drain voltage (?v drain ? in figure 23) is essentially floating and naturally begins to drop. if the switch is turned on at this moment, then crm operation will be achieved. to measure this high voltage directly on the inductor is generally not economical or practical. rather, a smaller winding is taken off of the boost inductor. this winding, called the zero current detector (zcd) winding, gives a scaled version of the inductor output and is more useful to the controller. figure 28. voltage waveforms for zero current detection drv winding drain v out v cl(pos) v zcdh v zcdl zcd v cl(neg) v zcd(on) v zcd(off) figure 28 gives typical operating waveforms with the zcd winding. when the drive is on, a negative voltage appears on the zcd winding. and when the drive is off, a positive voltage appears. when the inductor current drops to zero, then the zcd voltage falls and starts to ring around zero volts. the ncp1607 detects this falling edge and starts the next driver on time. to ensure that a zcd event has truly occurred, the ncp1607?s logic (figure 29) waits for the zcd pin voltage to rise above v zcdh (2.1 v typical) and then fall below v zcdl (1.6 v typical). in this way, crm operation is easily achieved. figure 29. implementation of the zcd winding zcd + ? + + ? + vcl(pos) clamp shutdown demag vcl(neg) active clamp + ? + reset dominant latch r q s drive r sense r zcd v dd v in n zcd q n b v zcdh v zcdl v sdl
ncp1607 www. onsemi.com 14 to prevent negative voltages on the zcd pin, the pin is internally clamped to v cl(neg) (600 mv typical) when the zcd winding is negative. similarly, the zcd pin is clamped to v cl(pos) (5.7 v typical), when the voltage rises too high. because of these clamps, a resistor (r zcd in figure 29) is necessary to limit the current from the zcd winding to the zcd pin. at startup, there is no energy in the zcd winding and therefore no voltage signal to activate the zcd comparators. this means that the driver could never turn on. therefore, to enable the pfc stage to startup under these conditions, an internal watchdog timer is integrated into the controller. this timer turns the drive on if the driver has been off for more than 180 s (typical). this feature is deactivated during a fault mode (ovp , uvp, or shutdown), and reactivated when the fault is removed. startup generally, a resistor connected between the ac input and v cc (pin 8) charges the v cc capacitor to the v cc(on) level (12 v typical). because of the very low consumption of the ncp1607 during this stage (< 40 a), most of the current goes directly to charging up the v cc capacitor. this provides faster startup times and reduced standby power dissipation. when the v cc voltage exceeds the v cc(on) level, the internal references and logic of the ncp1607 turn on. the controller has an undervoltage lockout (uvlo) feature which keeps the part active until v cc drops below v cc(off) (9.5 v typical). this hysteresis allows ample time for the auxiliary winding to take over and supply the necessary power to v cc (figure 30). figure 30. typical v cc startup waveform v cc v cc(on) v cc(off) when the pfc pre?converter is loaded by a switch mode power supply (smps), then it is often preferable to have the smps controller startup first. the smps can then supply the ncp1607 v cc directly. advanced controllers, such as the ncp1230 or ncp1381, can control when to turn on the pfc stage (see figure 31) leading to optimal system performance. this setup also eliminates the startup resistors and therefore improves the no load power dissipation of the system. figure 31. ncp1607 supplied by a downstream smps controller (ncp1230) 1 7 6 5 2 3 4 ncp1607 + + + + 1 7 6 5 2 3 4 ncp1230 88 v cc + c bulk d boost pfc_v cc quick start and soft start at startup, the error amplifier is enabled and control is pulled up to v eal (2.1 v typical). this is the lowest level of control voltage which produces output drives. this feature, called ?quick start,? eliminates the delay at startup associated with charging the compensation network to its minimum level. this also produces a natural ?soft?start? mode where the controller?s power ramps up from zero to the required power (see figure 32).
ncp1607 www. onsemi.com 15 figure 32. startup timing diagram showing the natural soft start of the control pin fb control natural soft start v cc i m v eal v out v cc(off) v cc(on) v ref output driver the ncp1607 includes a powerful output driver capable of peak currents of source 500 ma / sink 800 ma. this enables the controller to ef ficiently drive power mosfets for medium power (up to 300 w) applications. additionally, the driver stage is equipped with both passive and active pull down clamps (figure 33). the clamps are active when v cc is off and force the driver output to well below the threshold voltage of a power mosfet. figure 33. output driver stage and pull down clamps uvlo drv gnd + ? + drv in uv dd v cc v dd v ddgd v ddreg uvlo overvoltage protection the low bandwidth of the feedback network makes active pfc stages very slow systems. one consequence of this is the risk of huge overshoots in abrupt transient phases (startup, load steps, etc.). for reliable operation, it is critical that some form of overvoltage protection (ovp) effectively prevents the output voltage from rising too high. the ncp1607 detects these excessive v out levels and disables the driver until the output voltage returns to nominal levels. this keeps the output voltage within an acceptable range. the limit is adjustable so that the overvoltage level can be optimally set. the level must not be so low that it is triggered by the 100 or 120 hz ripple of the output voltage, but it must be low enough so as not to require a larger voltage rating of the output capacitor. figure 34 depicts the operation of the ovp circuitry.
ncp1607 www. onsemi.com 16 figure 34. ovp and uvp circuit blocks fb control + ? e/a + ? measure + + uvp fault dynamic ovp v eah clamp static ovp is triggered when clamp is activated. v eal clamp static ovp enable (enable ea) r out2 r out1 c comp v dd i control > i ovp i control v out i control v control r fb i rout1 i rout2 v ref v uvp i rfb when the output voltage is in steady state equilibrium, r out1 and r out2 regulate the fb voltage to v ref . during this equilibrium state, no current flows through the compensation capacitor (c comp shown in figure 34). these facts allow the following equations to be derived: ? the r out1 current is: i rout1 v out v ref r out1 (eq. 7) ? the r eq current is: i eq v ref r eq i rout2 i fb (eq. 8) ? and since no current flows through c comp , i rout1 v out v ref r out1 v ref r eq (eq. 9) under stable conditions, equations 7 through 9 are true. conversely, when v out is not at the target voltage, the output of the error amplifier sinks or sources the current necessary to maintain v ref on pin 1. in the case of an overvoltage condition: ? the error amplifier maintains v ref on pin 1, and the r eq current remains the same as the steady state value: i eq v ref r eq (eq. 10) ? the r out1 current is increased and is calculated using equation 11: i rout1 v out(ovp) v ref r out1 v out v out v ref r out1 (eq. 11 ) where v out is the output voltage excess. ? the error amplifier sinks: i control i rout1 i eq v out v out v ref r out1 v re f r eq (eq. 12 ) the combination of equations 2 and 12 yield a simple expression of the current sunk by the error amplifier: i control v out r out1 the current absorbed by pin 2 (i control ) is proportional to the output voltage excess. the circuit senses this current and disables the drive (pin 7) when i control exceeds i ovp (10.4 a typical). the ovp threshold is calculated using equation 13. v out(ovp) v out r out1 i ovp (eq. 13) the ovp limit is set by adjusting r out1 . r out1 is calculated using equation 14. r out1 v out(ovp) v out i ovp (eq. 14) for example, if 440 v is the maximum output voltage and 400 v is the target output voltage, then r out1 is calculated using equation 14. r out1 440 400 10.4 3.846 m if r out1 is selected as 4 m ,, then v out(ovp) = 442 v.
ncp1607 www. onsemi.com 17 static overvoltage protection if the ovp condition lasts for a long time, it may happen that the error amplifier output reaches its minimum level (i.e. control = v eal ). it would then not be able to sink any current and maintain the ovp fault. therefore, to avoid any discontinuity in the ovp disabling effect, the circuit incorporates a comparator which detects when the lower level of the error amplifier is reached. this event, called ?static ovp?, disables the output drives. once the ovp event is over, and the output voltage has dropped to normal, then control rises above the lower limit and the driver is re?enabled (figure 35). figure 35. ovp timing diagram dynamic ovp static ovp drv i ovph i ovpl v eah v control v out v eal i control ncp1607 undervoltage protection (uvp) when the pfc stage is plugged in, the output voltage is forced to roughly equate the peak line voltage. the ncp1607 detects an undervoltage fault when this output voltage is unusually low, such that the feedback voltage is below v uvp (300 mv typical). in an uvp fault, the drive output and error amplifier (ea) are disabled. the latter is done so that the ea does not source a current which would increase the fb voltage and prevent the uvp event from being accurately detected. the uvp feature helps to protect the application if something is wrong with the power path to the bulk capacitor (i.e. the capacitor cannot charge up) or if the controller cannot sense the bulk voltage (i.e. the feedback loop is open). furthermore, the ncp1607 incorporates a novel startup sequence which ensures that undervoltage conditions are always detected at startup. it accomplishes this by waiting approximately 180 s after v cc reaches v cc(on) before enabling the error amplifier (figure 36). during this wait time, it looks to see if the feedback (fb) voltage is greater than the uvp threshold. if not, then the controller enters a uvp fault and leaves the error amplifier disabled. however, if the fb pin voltage increases and exceeds the uvp level, then the controller will start the application up normally. figure 36. the ncp1607?s startup sequence with and without a uvp fault fb control 2.5 v uvp uvp wait uvp wait v uvp v eah v eal v out v out v cc(off) v cc(on) v cc uvp fault is ?removed? the voltage on the output which exits a uvp fault is given by: v out(uvp) r out1 r eq r eq v uvp (eq. 15) if r out1 = 4 m and r eq = 25.16 k , then the v out uvp threshold is 48 v. this corresponds to an input voltage of approximately 34 vac. open feedback loop protection the ncp1607 features comprehensive protection against open feedback loop conditions by including ovp, uvp, and floating pin protection (fpp). figure 37 illustrates three conditions in which the feedback loop is open. the corresponding number below describes each condition shown in figure 37. 1. uvp protection: the connection from resistor r out1 to the fb pin is open. r out2 pulls down the fb pin to ground. the uvp comparator detects a uvp fault and the drive is disabled. 2. ovp protection: the connection from resistor r out2 to the fb pin is open. r out1 pulls up the fb pin to the output voltage. the esd diode clamps the fb voltage to 10 v and r out1 limits the current into the fb pin. the v eal clamp detects a static ovp fault and the drive is disabled. 3. fpp protection: the fb pin is floating. the internal pulldown resistor r fb pulls down the fb voltage below the uvp threshold. the uvp comparator detects a uvp fault and the drive is disabled.
ncp1607 www. onsemi.com 18 uvp and ovp protect the system from low bulk voltages and rapid operating point changes respectively, while the fpp protects the system against floating feedback pin conditions. if fpp is not implemented and a manufacturing error causes the feedback pin to float, then the feedback voltage is d ependent on the coupling within the system and the surrounding environment. the coupled feedback voltage may be within the regulation limits (i.e. above the uvp threshold, but below v ref ) and cause the controller to deliver excessive power. the result is that the output voltage rises until a component fails due to the voltage stress. the tradeoff for including fpp is that the value of r fb causes an error in the output voltage. the output voltage including the error caused by r fb (v out ) is calculated using equation 16: v out v out r out1 v ref r fb (eq. 16) using the values from the ovp calculation, the output voltage including the error caused by r fb is equal to: v out 400 4m 2.5 4.7 m 402 v the error caused by r fb is compensated by adjusting r out2 . the parallel combination of r fb and r out2 form an equivalent resistor r eq that is calculated using equation 17. r eq r out1 v ref v out v ref (eq. 17) r eq 4m 2.5 400 2.5 25.16 k r eq is used to calculate r out2 . r out2 r eq r fb r fb r eq (eq. 18) r out2 25.16 k 4.7 m 4.7 m 25.16 k 25.29 k the compensated output voltage is calculated using equation 19. v out v ref r out1 r out2 r out2 r out1 v ref r fb (eq. 19 ) v out 2.5 4m 25.29 k 25.29 k 4m 2.5 4.7 m 400 v control e/a fb uvp static ovp fault dynamic ovp enable condition 2 condition 1 condition 3 figure 37. open feedback loop protection + - + + - + r fb c comp v control i control i control r out2 r out1 v out v eah clamp v dd v eal clamp measure static ovp is triggered when clamp is activated (enable ea) i control > i ovp v ref v uvp overcurrent protection (ocp) a dedicated pin on the ncp1607 senses the peak current and limits the driver on time if this current exceeds v cs(limit) . this level is 0.5 v (typical). therefore, the maximum peak current can be adjusted by changing r sense according to: i peak v cs(limit) r s (eq. 20) an internal leb filter (figure 38) reduces the likelihood of switching noise falsely triggering the ocp limit. this filter blanks out the first 250 ns (typical) of the current sense signal. if additional filtering is necessary, a small rc filter can be added between r sense and the cs pin.
ncp1607 www. onsemi.com 19 figure 38. ocp circuitry with optional external rc filter cs + ? + ocp leb drv optional r s v cs(limit) shutdown mode the ncp1607 allows for two methods to place the controller into a standby mode of operation. the fb pin can be pulled below the uvp level (300 mv typical) or the zcd pin can be pulled below the v sdl level (200 mv typical). if the fb pin is used for shutdown (figure 39 (a)), care must be taken to ensure that no significant leakage current exists on the shutdown circuitry. this could impact the output voltage regulation. if the zcd pin is used for shutdown (figure 39(b)), then any parasitic capacitance created by the shutdown circuitry will add to the delay in detecting the zero inductor current event. figure 39. shutting down the pfc stage by pulling fb to gnd (a) or pulling zcd to gnd (b) 1 4 3 2 8 5 6 7 ncp1607 shutdown shutdown r zcd r out2 r out1 v out c comp 1 4 3 2 8 5 6 7 ncp1607 figure 39(a) figure 39(b) l boost fb control ct cs gnd zcd drv v cc fb control ct cs gnd zcd drv v cc to activate the shutdown feature on zcd, the internal clamp must first be overcome. this clamp will draw a maximum of i cl(neg) (5.0 ma maximum) before releasing and allowing the zcd pin voltage to drop low enough to shutdown the part (figure 40). after shutdown, the comparator includes approximately 90 mv of hysteresis to ensure noise free operation. a small current source (70 a typical) is also activated to pull the unit out of the shutdown condition when the external pull down is released. figure 40. shutdown comparator and current draw to overcome negative clamp shutdown 5 ma ~1 v v sdl v sdh i zcd v cl(neg) ~70 a controller disabled controller enabled
ncp1607 www. onsemi.com 20 application information on semiconductor provides an electronic design tool, a demonstration board and an application note to facilitate the design of the ncp1607 and reduce development cycle time. all the tools can be downloaded or ordered at www.onsemi.com. the electronic design tool allows the user to easily determine most of the system parameters of a boost pre?converter. the demonstration board is a boost pre?converter that delivers 100 w at 400 v. the circuit schematic is shown in figure 41. the pre?converter design is described in application note and8353/d. figure 41. application board circuit schematic c3 d1 + + u1 ncp1607 5 zcd 3 ct 6 gnd 4 cs 8 vcc 7 drv 1 fb 2 control j3 j1 l2 f1 c2 q1 bridge t ntc j2 l1 r1 c1 r start1 r start2 l boost d boost cv cc d aux dv cc r zcd cv cc 2 d drv r drv c zcd r ctup2 r ctup1 r o1a r o1b c bul - k r out2b r out2a c in c comp1 r comp2 c comp c t1 c t2 c cs r cs r s3 r s2 r s1 r ct
ncp1607 www. onsemi.com 21 boost design equations components are identified in figure 1 rms input current iac p out vac (the efficiency of only the boost pfc stage) is generally in the range of 90 ? 95% maximum inductor peak current i pk(max) 2 2 p out vac ll where vac ll is the minimum line in- put voltage. i pk(max) occurs at the lowest line voltage. inductor v alue l
2 vac 2 v out 2 vac v out vac i pk(max) f sw(min) f sw(min) is the minimum desired switching frequency. the maximum l must be calculated at low line and high line. maximum on time t on(max) 2 l p out vac ll 2 the maximum on time occurs at the lowest line voltage and maximum output power. off time t off t on v out vac sin( ) 2 1 the off time is greatest at the peak of the ac line voltage and approaches zero at the ac line zero crossings. theta ( ) represents the angle of the ac line voltage. frequency f sw vac 2 2 l p out 1 vac | sin | 2 v out pin 3 capacitor ct 2 p out l i charge vac 2 v ctmax i charge and v ctmax are given in the ncp1607 specification table. boost turns to zcd turns ratio n b :n zcd
v out vac hl 2 v zcdh where vac hl is the maximum line input voltage. the turns ratio must be low enough so as to trigger the zcd comparators at high line. resistor from zcd wind- ing to the zcd pin (pin 5) r zcd vac hl 2 i cl(neg) (n b :n zcd ) r zcd must be large enough so that the shutdown comparator is not inad- vertently activated. boost output voltage v out v ref r out1 r eq r eq r eq r out2 r fb r out2 r fb maximum v out voltage prior to ovp activation and the necessary r out1 and r out2 . v out(ovp) v out i ovp r out1 r out1 v out(ovp) v out i ovp r eq r out1 v ref v out v ref r out2 r eq r fb r fb r eq i ovp is given in the ncp1607 spe- cification table. minimum output voltage necessary to exit under- voltage protection (uvp) v out(uvp) v uvp r out1 r eq r eq v uvp is given in the ncp1607 spe- cification table. bulk cap ripple v ripple(pk?pk) p out c bulk 2 f line v out use f line = 47 hz for worst case at universal lines. the ripple must not exceed the ovp level for v out . inductor rms current i l(rms) 2 p out 3 vac ll boost diode rms current i d(rms)max 4 3 2 2 p out vac ll v out
ncp1607 www. onsemi.com 22 boost design equations components are identified in figure 1 mosfet rms current i m(rms)max 2 3 p out vac ll 1 8 2 vac ll 3 v out mosfet sense resistor r s v cs(limit) i pk(max) p rs i m(rms) 2 r s v cs(limit) is given in the ncp1607 specification table. bulk capacitor rms current i c(rms) 32 2 p out 2 9 vac ll v out 2 (i load(rms) ) 2 type 1 c comp c comp 10 g 20 4 f line r out1 g is the desired attenuation in deci- bels (db). typically it is 60 db.
ncp1607 www. onsemi.com 23 package dimensions soic?8 nb case 751?07 issue aj seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751?01 thru 751?06 are obsolete. new standard is 751?07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ?x? ?y? g m y m 0.25 (0.010) ?z? y m 0.25 (0.010) z s x s m 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 mm inches scale 6:1 *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting t echniques reference manual, solderrm/d. soldering footprint* on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent? marking.pdf. scillc reserves the right to make changes without further notice to any product s herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its paten t rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or othe r applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death ma y occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidi aries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of per sonal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. sci llc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 ncp1607/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your lo cal sales representative

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